With reference to FIG. 1, a conventional power switch driving circuit is shown. In operation, a received control signal (e.g., a pulse-width modulation [PWM] signal) can be converted to a pair of differential signals (e.g., TR+ and TR−). Differential signals TR+ and TR− can be input to control nodes of NMOS transistors N1 and N2, respectively. Also, driving ability can be enhanced by latched comparator 101 that includes NMOS transistors N3 and N4, and PMOS transistors P1-P4. Example driving signals for N1-N4 can be seen in FIG. 2, where driving signal “gate” for the power switch can be generated by controlling the MOS transistors. However, drawbacks of this approach include latched comparator 101 having four PMOS transistors P1-P4, thereby resulting in a relatively larger layout area and increased product costs.